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September 2006 rev 0.3 3.3V CMOS Dual 1-To-5 Clock Driver
Features
* * * * * * * * * * * * * Advanced CMOS Technology Guaranteed low skew < 200pS (max) Very low propagation delay < 2.5nS (max) Very low duty cycle distortion < 270pS (max) Very low CMOS power levels Operating frequency up to 166MHz TTL compatible inputs and outputs Inputs can be driven from 3.3V or 5V components Two independent output banks with 3-state control 1:5 fanout per bank "Heartbeat" monitor output VCC = 3.3V 0.3V Available in SSOP and QSOP Packages
PCS2P3805E
Functional Description
The PCS2P3805E is a 3.3V clock driver built using advanced CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The PCS2P3805E offers low capacitance inputs. The PCS2P3805E is designed for high speed clock distribution where signal quality and skew are critical. The PCS2P3805E also allows single point-to-point transmission line driving in applications such as address distribution, where one signal must be distributed to multiple receivers with low skew and high signal quality.
Block Diagram
Pin Diagram
OEA INA 5 OA1 - OA5
VCCA
OA1
1 2 3 4 5 6 7 8 9 10
20 19 18 17
VCCB OB1 OB2 OB3 GNDB OB4 OB5 MON OEB INB
OA2 OA3 GNDA
PCS2P3805E
16 15 14 13 12 11
INB OEB
5
OB1 - OB5
OA4 OA5 GNDQ
MON OEA INA
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
September 2006 rev 0.3
Pin Description Pin #
9,12 10,11 2,3,4,6,7 19,18,17,15,14 1 20 5 16 8 13
PCS2P3805E
Pin Names
OEA, OEB INA, INB OA1-OA5 OB1-OB5 VCCA VCCB GNDA GNDB GNDQ MON
Description
3-State Output Enable Inputs (Active LOW) Clock Inputs Clock Outputs from Bank A Clock Outputs from Bank B Power supply for Bank A Power supply for Bank B Ground for Bank A Ground for Bank B Ground Monitor Output
Function Table1 Inputs OEA, OEB
L L H H
Note: 1 H = HIGH; L = LOW; Z = High-Impedance
Outputs INA, INB
L H L H
OAn, OBn
L H Z Z
MON
L H L H
Capacitance (TA = +25C, f = 1.0MHz) Symbol
CIN COUT
Parameter1
Input Capacitance Output Capacitance
Conditions
VIN= 0V VOUT = 0V
Typ
3 -
Max
4 6
Unit
pF pF
Note: 1 This parameter is measured at characterization but not tested.
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.3
Absolute Maximum Ratings1 Symbol
VCC VI VO TJ TSTG TDV
PCS2P3805E
Description
Input Power Supply Voltage Input Voltage Output Voltage Junction Temperature Storage Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B)
Max
-0.5 to +4.6 -0.5 to +5.5 -0.5 to VCC+0.5 150 -65 to +165 2
Unit
V V V C C KV
Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability.
DC Electrical Characteristics over Operating Range
Following Conditions Apply Unless Otherwise Specified Industrial: TA = -40C to +85C, VCC = 3.3V 0.3V
Symbol
VIH VIL IIH IIL IOZH IOZL VIK IODH IODL IOS
Parameter
Input HIGH Level Input LOW Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Outputs Pins) Clamp Diode Voltage Output HIGH Current Output LOW Current Short Circuit Current VCC= Max. VCC= Max. VCC= Max.
Test Conditions1
Min
2 -0.5
Typ2
-0.7 -74 90 -135 3 3 0.3 0.2 -
Max
5.5 0.8 1 1 1 1 -1.2 -180 200 -240 0.4 0.4 0.2
Unit
V V
VI = 5.5V VI = GND VO = VCC VO = GND
3,4
A
VCC= Min., IIN = -18mA VCC= 3.3V, VIN = VIH or VIL, VO = 1.5V
V mA mA mA
-45 50 -60
VCC= 3.3V, VIN = VIH or VIL, VO = 1.5V3,4 VCC= Max., VO = GND VCC= Min. VIN = VIH or VIL
3,4
IOL= 12mA VOH Output HIGH Voltage IOH= -8mA IOH= -100A IOL= 12mA VOL Output LOW Voltage VCC= Min. VIN = VIH or VIL IOL= 8mA IOL= 100A
2.45 2.4
5
V
VCC - 0.2 -
V
Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, 25C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC -0.6V at rated current.
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.3
Power Supply Characteristics Symbol
ICCL ICCH ICCZ ICC ICCD
PCS2P3805E
Parameter
Quiescent Power Supply Current Power Supply Current per Input HIGH
Test Conditions1
VCC = Max. VIN = GND or VCC VCC = Max. VIN = VCC -0.6V VIN = VCC VIN = GND VIN = VCC VIN = GND VIN = VCC -0.6V VIN = GND VIN = VCC VIN = GND VIN = VCC -0.6V VIN= GND
Min
-
Typ2
0.1 45 80
Max
30 300 120
Unit
A A A/MHz
VCC= Max. Dynamic Power Supply CL= 15pF 3 Current per Output All Outputs Toggling VCC= Max. CL= 15pF All Outputs Toggling fi = 133MHz VCC= Max. CL= 15pF All Outputs Toggling fi = 166MHz
-
210 210 260 260
240 240 mA 310 310
IC
Total Power Supply 4 Current
Notes: 1. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 4. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.3
Switching Characteristics Over Operating Range - PCS2P3805E3,4 Symbol
tPLH tPHL tR tF tSK(O) tSK(P) tSK(PP) tPZL tPZH tPLZ tPHZ fMAX
PCS2P3805E
Parameter
Propagation Delay INA to OAn, INB to OBn Output Rise Time (Measured from 0.7V to 1.7V) Output Fall Time (Measured from 1.7V to 0.7V) Same device output pin to pin skew5 Pulse skew6,9 Part to part skew7 Output Enable Time OEA to OAn, OEB to OBn Output Disable Time OEA to OAn, OEB to OBn Input Frequency
Conditions1,8
Min2
0.5 -
Max
2.5 1 1 200 270 550 5.2 5.2 166
Unit
nS nS nS pS pS pS nS nS MHz
CL= 15pF f 166MHz
-
Notes: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH , tPHL and tSK(O) are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min and Max limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 5. Skew measured between all outputs under identical transitions and load conditions. 6. Skew measured is difference between propagation delay times tPHL and tPLH of same outputs under identical load conditions. 7. Part to part skew for all outputs given identical transitions and load conditions at identical VCC levels and temperature. 8. Airflow of 1m/s is recommended for frequencies above 133MHz. 9. This parameter is measured using f = 1MHz.
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.3
Test Circuits and Waveforms
VCC 6V
PCS2P3805E
Open GND 500
VIN Pulse Generator RT D.U.T RL
VOUT CL
500
Enable and Disable Time Circuit
VCC INPUT tPLH1 VIN Pulse Generator RT D.U.T RL VOUT CL OUTPUT 2 tPLH2 tPHL2 OUTPUT 1 tSK(O) tSK(O) tPHL1 3V 1.5V 0V VOH 1.5V VOL VOH 1.5V VOL tSK(O) = | tPLH2 - tPLH1 | or | tPHL2 - tPHL1 |
CL = 15pF Test Circuit
Output Skew - tSK(o)
Switch Position Test
Disable Low Enable Low Disable High Enable High
Test Conditions Switch
6V GND
Symbol
CL RT RL t R / tF
Definitions:
VCC = 3.3V 0.3V
15 ZOUT of pulse generator 33 1 (0V to 3V or 3V to 0V)
Unit
pF nS
CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. tR / tF = Rise/Fall time of the input stimulus from the Pulse Generator.
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.3
Test Circuits and Waveforms
ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY SWITCH LOW CLOSED tPZH OUTPUT NORMALLY HIGH SWITCH OPEN 1.5V VOL VOH 1.5V tPHZ 0.3V VOH VOL tPLZ 0.3V DISABLE 3V 1.5V 0V VOH VOL Package 2 OUTPUT tPLH2 Package 1 OUTPUT tSK(PP) INPUT tPLH1
PCS2P3805E
3V tPHL1 1.5V 0V VOH 1.5V VOL VOH 1.5V VOL
tSK(PP)
tPHL2
tSK(PP) = | tPLH2 - tPLH1 | or | tPHL2 - tPHL1 |
Enable and Disable Times
Note: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
Part-to- Part Skew
Note: Part-to- Part Skew is for package and speed grade.
3V INPUT tPLH OUTPUT tR tF tPHL 2.0V 0.8V 1.5V 0V VOH 1.5V VOL OUTPUT tSK(P) = | tPLH - tPLH | INPUT tPLH tPHL
3V 1.5V 0V VOH 1.5V VOL
Pulse Skew Propagation Delay
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.3
Package Information 20-lead SSOP ( 209 mil )
PCS2P3805E
Dimensions Symbol
A A1 A2 D c E E1 L L1 b R1 a e
Inches Min Max
.... 0.002 0.065 0.275 0.004 0.295 0.197 0.021 0.009 0.004 0 0.079 ... 0.073 0.291 0.010 0.319 0.220 0.037 0.015 .... 8
Millimeters Min Max
... 0.05 1.65 7.00 0.09 7.50 5.00 0.55 0.22 0.09 0 2.0 ..... 1.85 7.40 0.25 8.10 5.60 0.95 0.38 .... 8
0.050 REF
1.25 REF
0.0197 BASE
0.65 BASE
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.3
PCS2P3805E
20-lead QSOP
Symbol
A A1 b c D E e H h L S a
Dimensions Inches Millimeters Min Max Min Max
0.060 0.004 0.009 0.007 0.337 0.150 0.230 0.010 0.016 0.056 0 0.068 0.008 0.012 0.010 0.344 0.157 0.244 0.016 0.035 0.060 8 1.52 0.10 0.23 0.18 8.56 3.81 5.84 0.25 0.41 1.42 0 1.73 0.20 0.30 0.25 8.74 3.99 6.20 0.41 0.89 1.52 8
0.025 BSC
0.64 BSC
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.3
Ordering Information Part Number
PCS2P3805EG-20-AR PCS2P3805EG-20-AT PCS2P3805EG-20-DR PCS2P3805EG-20-DT PCS2I3805EG-20-AR PCS2I3805EG-20-AT PCS2I3805EG-20-DR PCS2I3805EG-20-DT
PCS2P3805E
Marking
2P3805EG 2P3805EG 2P3805EG 2P3805EG 2I3805EG 2I3805EG 2I3805EG 2I3805EG
Package Type
20-Pin SSOP, TAPE & REEL, Green 20-Pin SSOP, TUBE, Green 20-Pin QSOP, TAPE & REEL, Green 20-Pin QSOP, TUBE, Green 20-Pin SSOP, TAPE & REEL, Green 20-Pin SSOP, TUBE, Green 20-Pin QSOP, TAPE & REEL, Green 20-Pin QSOP, TUBE, Green
Temperature
Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial
Device Ordering Information
PCS2P3805E
G-20-AT
R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70
G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.3
PCS2P3805E
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com
Copyright (c) PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2P3805E Document Version: 0.3
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
(c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
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